Following increased interest in the Data Vortex solution, we have decided to include Frequently Asked Questions (FAQs) from individuals interested in programming, purchasing, and incorporating the Data Vortex network solution into existing and future systems. Please fill out the form at the bottom of the page to ask any questions.


Q: Within the context of a Data Vortex computer, what makes up a compute node?

A:  The compute nodes used in current generation Data Vortex systems are Intel-based, SuperMicro servers. Each server is populated with either one or two high-end Intel Xeon processors. Each processor has 128 GB of DDR DRAM for local application usages. Vortex Interface Cards (VICs) are installed into the servers so each CPU has its own network interface. Additionally, each compute node has an InfiniBand card to support porting legacy software that relies on InfiniBand technology.

Q: How large can the current generation of Data Vortex computers be built?

A: In the current generation, 1-level systems are scalable up to 64 nodes (DV202 – DV206). 2-level systems are scalable up to 2,048 nodes (DV207-DV211). 3-level systems are scalable up to 65,653 nodes (DV212 – DV216). The Data Vortex 2-level switch has already been designed and implemented, successfully running benchmarks on our two-level test bed platform, KARMA, in Boulder, Colorado. Sample images of 2-level Data Vortex systems are shown below.

Q: What makes up the Data Vortex network?

A:  The Data Vortex network consists of Data Vortex switches arranged in a fat tree topology and Data Vortex Interface Controllers (VICs) connecting the network to the servers (US Patent 9253248).  The Data Vortex switches randomize data that is sent up the tree and route data that is sent down the tree. The VICs connect the servers to a number of independent networks (There are 16 networks in present DV-enabled computers). The VICs are designed expressly to connect Data Vortex switches and servers. The VICs contain logic and SRAM memory.

The switch consists of a richly connected set of rings arranged in levels. Data, in the form of packets, enters the switch in the top-level ring. Data then travels around a ring on a given level, or travels between a ring on a given level, down to a ring on the next lower level. Data on the top level is able to access all output ports. Data on the next level is able to access only half of the output ports. This process continues so that on the bottom level, the target of the packet is achieved. The payload of a packet contains information including the target output port address (US Patent 9479858). In today’s Data Vortex computers, the switches are built on Altera Stratix V FPGAs.

General System Level FAQs:

Q: What OS does the system run?

A: CentOS 7.2.1511

Q: What scheduler is used?

A: Slurm 14.03.10

Q: How is the system managed?

A: Cobbler & Ansible

Q: How is the user environment managed?

A: Lmod, a Lua based module system.

General Programming FAQs:

Q: What languages are supported?

A: C, OpenMP, pthreads

Q: Does the system support mixed mode programming?

A: Yes, software can be written to take advantage of both the Data Vortex network and legacy MPI over Infiniband

Q: What is the default compiler?

A: gcc 4.8.5


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